1. Field of the Invention
The present invention relates to a technology for performing device isolation of a semiconductor device by using a CMP (Chemical Mechanical Polishing) method.
2. Description of the Related Art
As a device isolation technique used for a semiconductor device, there has been known, for example, an STI (Shallow Trench Isolation) technology. In the STI technology, device isolation is carried out by shallow trenches defined in the surface of a semiconductor substrate.
One example of a device isolating process using the STI technology will be explained below with reference to FIGS. 8A–8D and 9A–9B.
(1) A protective oxide film 802 having a thickness of about 15 nm is formed on the surface of a silicon substrate 801. Subsequently, a silicon nitride (SiN) film 803 is formed on the surface of the protective oxide film 802 by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method. Further, resist patterns 804 are formed on a device forming region of the silicon nitride film 803 by using a normal photolithography technology (see FIG. 8(A)).
(2) Dry etching using the resist patterns 804 as masks is effected to sequentially etch the silicon nitride film 803, the protective oxide film 802 and the silicon substrate 801, thereby forming trenches 805. Thereafter, the resist patterns 804 are removed (see FIG. 8(B)).
(3) A rounding oxidizing treatment is effected on inner wall surfaces of the trenches 805. Consequently, oxide films 806 are formed. The oxide films 806 make it possible to prevent damage to the inner wall surfaces, the occurrence of crystal defects and contamination at the time that an oxide film 807 is formed in a subsequent process. Further, since the corners of upper ends of the trenches 805 can be rounded by the corresponding oxide films 806, the oxide film 807 can be formed on the corners with no clearance.
(4) Next, the oxide film 807 is formed by, for example, a CVD (Chemical Vapor Deposition) method. Thus, the oxide film 807 is charged into the trenches 805 and covers the surface of the silicon nitride film 803 (see FIG. 8(C)).
(5) Subsequently, the CVD oxide film 807 is polished by the CMP method until the surface of the silicon nitride film 803 is exposed (see FIG. 8(D)). As an abrasive, for example, a silica slurry (abrasive containing grinding particles, which is made of a silica material) can be used.
(6) Afterwards, the surface of the CVD oxide film 807 is etched in such a manner that the upper surface of the CVD oxide film 807 becomes close to the surface of the silicon substrate 801 (see FIG. 9(A)).
(7) Then, the silicon nitride film 803 is removed using a solution of thermal phosphoric acid and the protective oxide film 802 is removed using hydrofluoric acid (see FIG. 9(B)).
Here, it is important to control the amount of polishing by a CMP process step (see above process step (5)) with high accuracy with a view toward improving yields and reliability of the semiconductor device.
However, it was very difficult to control the polishing amount of CMP with high accuracy. This is because the polishing speed of CMP in a given region on the silicon substrate 801 depends not only on underlying conditions in a region to be polished but also on underlying conditions in a region around the polished region. Therefore, the section of the silicon substrate 801 has heretofore been analyzed after the CMP process step by use of an SEM (Scanning Electron Microscope). However, although the method for analyzing the section by the SEM is capable of accurately recognizing the remaining film thickness of the silicon nitride film 803, it causes a breakdown in the silicon substrate 801 and needs a large number of processes and much time for analysis.
The dependence of the polishing speed on the underlying base can also be reduced to some extent by using a CeO (cesium oxide, i.e., ceria) slurry as an abrasive. However, when a region in which an active pattern density (proportion of area occupied by device forming regions) is extremely small, exists, it becomes difficult to control the accurate remaining film thickness of the silicon nitride film 803 in reverse. This is because when the ceria slurry is used, the polishing speed becomes very fast. Therefore, there is a possibility that the silicon nitride film 803 will disappear perfectly in the region in which the active pattern density is extremely small. Due to such a reason, a semiconductor integrated circuit should be designed in such a manner that the region in which the active pattern density is extremely small, does not exist when the ceria slurry is used. However, the addition of such a design condition will increase the load on design. Additionally, only the appropriateness of the design condition might encounter difficulties in controlling the polishing amount of CMP with high accuracy.
As a technology for improving the polishing accuracy of CMP, there have heretofore been known ones disclosed in, for example, the following patent documents 1 and 2. However, both of these show techniques aimed at improving the polishing accuracy when a film formed on wiring patterns is planarized by CMP. It is difficult to apply the present technique to a device isolating process. In the following patent documents 1 and 2, dummy patterns are formed to improve the smoothness of the film formed on the wiring patterns. Thus, when one attempts to apply the technologies of the patent documents 1 and 2 to the above-described device isolating processes (see FIGS. 8 and 9), dummy trenches are eventually formed. However, the formation of the dummy trenches will incur degradation of the rate of integration of the semiconductor device and an increase in complexity, thus resulting in unreality.    Japanese Unexamined Patent Publication No. 2002-140655    Japanese Unexamined Patent Publication No. 2002-342399